1. Field of the Invention
The invention generally relates to inspection marks for probe contacts adjacent wirebond connections, where the inspection marks comprise marks in the same conductor that is used as the probe pad and the wirebond connection.
2. Description of the Related Art
Wirebond connections are commonly used on the exterior layer of integrated circuits and chips to connect the circuitry within the chips to external devices and wiring boards. A wirebond connection comprises a conductive wire from an external device that is bonded to a conductive connection on the wafer or chip. It is common to form conductive probe contacts to which test probes and other similar devices make temporary contact when testing the chip. These probe contacts are formed next to the wirebond connection and are electrically connected to the wirebond connection.
Wirebond connections are being made with finer and finer pitch (e.g., are being made smaller and closer together). However, even as wirebond connections are being placed closer together, the probe contact (where the wafer tester touches down on the wafer) needs to be offset from the wirebond location in order to allow a good wirebond connection that has high yield and reliability. Failure to provide sufficient pristine pad surface area for the probe contact has shown to lead to yield and reliability failures. A visual inspection is typically performed by operators and a subjective decision is made as to whether the wirebond location has been damaged by the probe contact. Without a clearly marked inspection region, it is difficult to clearly determine whether the probe produced damage is outside the area in which the wirebond will be formed.